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1 copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com 24-bit, 96 khz stereo dac with volume control features ! 101 db dynamic range ! -91 db thd+n ! +3.0 v or +5.0 v power supply ! low clock-jitter sensitivity ! filtered line-level outputs ! on-chip digital de-e mphasis for 32, 44.1 and 48 khz ! atapi mixing ! digital volume control with soft ramp ? 94 db attenuation ? 1 db step size ? zero crossing click-free transitions ! popguard ? technology for control of clicks and pops ! 33 mw with 3.0 v supply description the cs4341 is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis and switched capacitor analo g filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. the cs4341 accepts data at audio sample rates from 4 khz to 100 khz, consumes very little power, and oper- ates over a wide power supply range. the features of the cs4341 are ideal for dvd players, cd players, set- top box and automotive systems. ordering information CS4341-KS 16-pin soic, -10 to 70 c cs4341-czz, lead free 16-pin tssop, -10 to 70 c cdb4341 evaluation board i volume control interpolation filter ? dac analog filter control port volume control interpolation filter analog filter serial port scl/cclk mutec ad0/cs aouta aoutb rst lrck sdata mclk sda/cdin ? dac external mute control sclk mixer 2 december '05 ds298f5 cs4341
cs4341 2 ds298f5 table of contents 1. characteristics and specifications ..................................................................................... 4 specified operating conditions .. ................ ................. ................ ................ ................ ........... 4 absolute maximum rating s ............... ................. ................ ................ ............. ............. ............. .4 analog characteristics (CS4341-KS/czz).......... ..................................................................... 5 combined interpolation & on-chip analog filter response........................................ 7 switching specifications - serial audio interface........................................................ 10 switching characteristics - internal serial clock ..................................................... 11 switching characteristics - control port interface (i2c?) ..................................... 12 switching characteristics - control port interface (spi?) ................................... 13 dc electrical characteristics.............................................................................................. 14 digital input characteristics ................................................................................................ 14 digital interface specifications........................................................................................... 14 2. pin description .......................................................................................................... ................... 15 3. typical connection diagram .............................................................................................. ... 16 4. applications .............................................................................................................. ..................... 17 4.1 sample rate range/operationa l mode ........................................................................................ 17 4.2 system clocking ........................................................................................................... ................ 17 4.2.1 internal serial clock mode .................. ............................................................................ .17 4.2.2 external serial clock mode .............................................................................................. 18 4.3 digital interface format . ................................................................................................. ............... 18 4.4 de-emphasis ............................................................................................................... ................. 19 4.5 power-up sequence ........................................................................................................ ............ 19 4.6 popguard ? transient control ........................................................................................................ 19 4.6.1 power-up ................................................................................................................ ......... 19 4.6.2 power-down .............................................................................................................. ....... 20 4.6.3 discharge time .......................................................................................................... ...... 20 4.7 mute control .............................................................................................................. ................... 20 4.8 grounding and power supply ar rangements ............................................................................... 20 4.9 control port interface .... ................................................................................................ ................ 20 4.9.1 rise time for control port clock ...................................................................................... 21 4.9.2 memory address pointer (m ap) ...................................................................................... 21 4.9.2a incr (auto map increment) .............. ................................................................ 21 4.9.2b map0-3 (memory address pointer) .. ................................................................ 21 4.9.3 i2c mode ................................................................................................................ .......... 21 4.9.3a i2c write ............................................................................................................ 22 4.9.3b i2c read ............................................................................................................ 22 4.9.4 spi mode ................................................................................................................ ......... 23 4.9.4a spi write ........................................................................................................... 23 5. register quick reference .................................................................................................. ..... 24 6. register description ...................................................................................................... ........... 25 6.1 mclk control (address 00h) ................................................................................................. ........ 25 6.2 mode control (address 01h) ................................................................................................. ......... 25 6.3 transition and mixing control (address 02h) .... ............................................................................ .27 6.4 channel a volume control (add ress 03h) ..................................................................................... 29 6.5 channel b volume control (add ress 04h) ..................................................................................... 29 7. parameter definitions ..................................................................................................... .......... 31 8. package dimensions ........................................................................................................ ............ 32
cs4341 ds298f5 3 8.1 soic ...................................................................................................................... ........................32 8.2 tssop ..................................................................................................................... .....................33 9. package thermal resistance ................................................................................................ .33 10. references ............................................................................................................... .....................34 11. revision history ......................................................................................................... .................34 list of figures figure 1. output test load .. ................................................................................................... ....................6 figure 2. maximum loading ...................................................................................................... ..................6 figure 3. single-speed stopband rejection ......... ............................................................................. .........8 figure 4. single-speed transition band ......................................................................................... ............8 figure 5. single-speed transition band (detail) ... ............................................................................. .........8 figure 6. single-speed passband ripple ................ ......................................................................... ..........8 figure 7. double-speed stopband rejection ........... ........................................................................... ........8 figure 8. double-speed transition band .............. ........................................................................... ...........8 figure 9. double-speed transition band (detail) ................................................................................ .......9 figure 10. double-speed passband ripple ............... ......................................................................... ..........9 figure 11. serial input timing (e xternal sclk) ................................................................................. .........10 figure 12. internal serial mode input timing ................................................................................... ...........11 figure 13. internal serial clock generation ........ ............................................................................ ............11 figure 14. control port timing - i2c mode ...................................................................................... ............12 figure 15. control port timing - spi mode ...................................................................................... ...........13 figure 16. typical connection dia gram .......................................................................................... ............16 figure 17. cs4341 formats 0-1 - i2s up to 24-bit data .......................................................................... ....18 figure 18. cs4341 format 2 - left just ified up to 24-bit data .................................................................. .18 figure 19. cs4341 formats 3-6 - rig ht justified ................................................................................ ........18 figure 20. de-emphasis curve ................................................................................................... ................19 figure 21. i2c buffer example .......................... ........................................................................ ...................21 figure 22. i2c write ........................................................................................................... ..........................22 figure 23. i2c read ............................................................................................................ .........................23 figure 24. control port timing, spi mode ....................................................................................... ...........23 figure 25. atapi block diagram ........................ ......................................................................... ...............29 list of tables table 1. cs4341 speed modes .................................................................................................... .................17 table 2. single-speed mode standa rd frequencies ................................................................................ .....17 table 3. double-speed mode standar d frequencies ................................................................................ ....17 table 4. internal sclk/lrck ratio .................... .......................................................................... .................18 table 5. digital interface form at .............................................................................................. ......................26 table 6. atapi decode.......................................................................................................... ........................28 table 7. example digital volume settings .......... ............................................................................. ..............30
cs4341 4 ds298f5 1. characteristics and specifications (min/max performance characteristics and specifications are gua ranteed over the specifi ed operating conditions. typical performance characteristics are derived from measurements taken at t a = 25 c.) specified operating conditions (all voltages with respect to agnd = 0 v.) absolute maximum ratings (agnd = 0 v; all voltages with respect to agnd. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.) notes: 1. any pin except supplies. parameters symbol min nom max units dc power supply nominal 3.3 v nominal 5.0 v va va 2.7 4.75 3.3 5.0 3.6 5.5 v v specified operating temperature -ks/czz (power applied) t a -10 - +70 c parameters symbol min max units dc power supply va -0.3 6.0 v input current (note 1) i in -10ma digital input voltage v ind -0.3 va+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs4341 ds298f5 5 analog characteristics (CS4341-KS/czz) (test conditions (unless otherwise specified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l =10k ? , c l = 10 pf (see figure 1).) parameter va = 5.0 v va = 3.0 v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range (note 2) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 93 96 - - 98 101 92 95 - - - - 89 92 - - 94 97 92 95 - - - - db db db db total harmonic distortion + noise (note 2) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -91 -78 -38 -90 -72 -32 -86 - - - - - - - - - - - -94 -74 -34 -91 -72 -32 -89 - - - - - db db db db db db double-speed mode fs = 96 khz dynamic range (note 2) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 93 96 - - 98 101 92 95 - - - - 89 92 - - 94 97 92 95 - - - - db db db db total harmonic distortion + noise (note 2) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -91 -78 -38 -90 -72 -32 -86 - - - - - - - - - - - -94 -74 -34 -91 -72 -32 -89 - - - - - db db db db db db
cs4341 6 ds298f5 analog characteristics (CS4341-KS/czz) (continued) notes: 2. one-half lsb of triangular pdf dither is added to data. 3. refer to figure 2. . parameters symbol min typ max units dynamic performance for all modes interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full-scale output volt age 0.6?va 0.7?va 0.8?va vpp output impedance - 100 - ? minimum ac-load resistance (note 3) r l -3-k ? maximum load capacitance (note 3) c l - 100 - pf aoutx agnd 3.3 f v out r l c l + figure 1. output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 2. maximum loading
cs4341 ds298f5 7 combined interpolation & on -chip analog filter response (the filter characteris- tics and the x-axis of the response plots have been normalized to the sample rate (fs) and can be referenced to the desired sample rate by multiplyin g the given charac teristic by fs.) notes: 4. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 5. de-emphasis is only available in single-speed mode. parameter min typ max unit single-speed mode - (4 khz to 50 khz sample rates) passband to -0.05 db corner to -3 db corner 0 0 - - 0.4535 0.4998 fs fs frequency response 10 hz to 20 khz -0.02 - +0.08 db stopband 0.5465 - - fs stopband attenuation (note 4) 50 - - db group delay - 9/fs - s passband group delay deviation 0 - 20 khz - 0.36/fs - s de-emphasis error (relative to 1 khz) fs = 32 khz (note 5) fs = 44.1 khz fs = 48 khz - - - - - - +0.2/-0.1 +0.05/-0.14 +0/-0.22 db db db double-speed mode - (50 khz to 100 khz sample rates) passband to -0.1 db corner to -3 db corner 0 0 - - 0.4621 0.4982 fs fs frequency response 10 hz to 20 khz -0.06 - +0.2 db stopband 0.577 - - fs stopband attenuation (note 4) 55 - - db group delay - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - 1.39/fs 0.23/fs - - s s
cs4341 8 ds298f5 figure 3. single-speed stopband rejectio n figure 4. single-speed transition band figure 5. single-speed transition band (d etail) figure 6. single-speed passband ripple figure 7. double-speed stopband rejection figure 8. double-speed transition band
cs4341 ds298f5 9 figure 9. double-speed transition band (d etail) figure 10. double-speed passband ripple
cs4341 10 ds298f5 switching specifications - serial audio interface parameters symbol min max units mclk frequency 1.024 51.2 mhz mclk duty cycle 45 55 % input sample rate single-speed mode double-speed mode fs fs 4 50 50 100 khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk frequency single-speed mode double-speed mode - - 128xfs 64xfs hz hz sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 11. serial input timing (external sclk)
cs4341 ds298f5 11 switching characteristics - internal serial clock notes: 6. the duty cycle must be 50% +/? 1/2 mclk period. 7. see section 4.2.1 for derived internal frequencies. parameters symbol min typ max units mclk frequency 1.024 - 51.2 mhz mclk duty cycle 45 - 55 % input sample rate single-speed mode double-speed mode fs fs 4 50 - - 50 100 khz khz lrck duty cycle (note 6) % sclk period (note 7) t sclkw -- s sclk rising to lrck edge t sclkr --s sdata valid to sclk rising setup time t sdlrs --ns sclk rising to sdata hold time mclk / lrck = 512, 256 or 128 t sdh --ns sclk rising to sdata hold time mclk / lrck = 384 or 192 t sdh --ns 1 sclk ---------------- t sclkw 2 ------------- - 1 512 () fs --------------------- -10 + 1 512 () fs --------------------- -15 + 1 384 () fs --------------------- -15 + sdata *internal sclk lrck sclkw t sdlrs t sdh t sclkr t figure 12. internal serial mode input timing * the sclk pulses shown are internal to the cs4341. sdata lrck mclk *internal sclk 1 n 2 n figure 13. internal serial clock generation * the sclk pulses shown are internal to the cs4341. n equals mclk divided by sclk
cs4341 12 ds298f5 switching characteris tics - control port interface (i2c ? ) notes: 8. data must be held for sufficient time to brid ge the transition time, t fc , of scl. 9. see ?rise time for control port clock? on page 21 for a recommended circuit to meet rise time specification. parameter symbol min max unit i2c mode scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 8) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl (note 9) t rc -25ns fall time of scl t fc -25ns rise time sda t rd -1s fall time of sda t fd -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 14. control port timing - i2c mode
cs4341 ds298f5 13 switching characteristi cs - control port interface (spi?) notes: 10. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 11. data must be held for sufficient time to bridge the transition time of cclk. 12. for f sclk < 1 mhz. parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 10) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl -ns cclk high time t sch -ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 11) t dh 15 - ns rise time of cclk and cdin (note 12) t r2 -100ns fall time of cclk and cdin (note 12) t f2 -100ns 1 mclk ----------------- 1 mclk ----------------- t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 15. control po rt timing - spi mode
cs4341 14 ds298f5 dc electrical characteristics (agnd = 0 v; all voltages wi th respect to agnd.) notes: 13. normal operation is defined as rst = hi with a 997 hz, 0 dbfs input sampled at the highest fs for each speed mode, and open outputs, unless otherwise specified. 14. power down mode is defined as rst = lo with all clocks and data lines held static. 15. valid with the recommended capacitor values on filt + and vq as shown in figure 16. increasing the capacitance will also increase the psrr. digital input c haracteristics (agnd = 0 v; all voltages with respect to agnd.) digital interface specifications (agnd = 0 v; all voltages with respect to agnd.) parameters symbol min typ max units normal operation (note 13) power supply current va = 5.0 v va = 3.0 v i a i a - - 15 11 18 14 ma ma power dissipation va = 5.0 v va = 3.0 v - - 75 33 90 42 mw mw power-down mode (note 14) power supply current va = 5.0 v va = 3.0 v i a - - 60 30 - - a a power dissipation va = 5.0 v va = 3.0 v - - 0.3 0.09 - - mw mw all modes of operation power supply re jection ratio (note 15) 1 khz 60 hz psrr - - 60 40 - - db db v q nominal voltage output impedance maximum allowable dc current source/sink - - - 0.45?va 250 0.01 - - - v k ? ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 250 0.01 - - - v k ? ma mutec low-level output voltage - 0 - v mutec high-level output voltage - va - v maximum mutec drive current - 3 - ma parameters symbol min typ max units input leakage current i in --10 a input capacitance - 8 - pf parameters symbol min max units 3.3 v logic (3.0 v to 3.6 v dc supply) high-level input voltage v ih 2.0 - v low-level input voltage v il -0.8v 5.0 v logic (4.75 v to 5.25 v dc supply) high-level input voltage v ih 2.0 - v low-level input voltage v il -0.8v
cs4341 ds298f5 15 2. pin description pin name # pin description rst 1 reset ( input ) - powers down device and resets registers to their default settings. sdata 2 serial audio data ( input ) - input for two?s complement serial audio data. sclk 3 serial clock ( input ) -serial clock for the serial audio interface. lrck 4 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 5 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. scl/cclk 6 serial control port clock ( input ) - serial clock for the control port interface. sda/cdin 7 serial control data i/o ( input/output ) - input/output for i2c data. input for spi data. ad0/cs 8 address bit / chip select ( input ) - chip address bit in i2c mode. control signal used to select the chip in spi mode. filt+ 9 positive voltage reference ( output ) - positive voltage reference for the internal sampling circuits. vq 10 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. ref_gnd 11 reference ground ( input ) - ground reference for the internal sampling circuits. aoutb aouta 12 15 analog outputs ( output ) - the full-scale analog output level is specified in the analog characteristics table. agnd 13 analog ground ( input ) va 14 power ( input ) - positive power for the analog, digital, and serial audio interface sections. mutec 16 mute control ( output ) - control signal for an optional mute circuit. 15 2 14 3 13 4 16 1 11 6 10 7 9 8 12 5 rst mutec sdata aouta sclk va lrck agnd mclk aoutb scl/cclk ref_gnd sda/cdin vq ad0/cs filt+
cs4341 16 ds298f5 3. typical connection diagram 13 serial audio data processor external clock mclk agnd aoutb cs4341 sdata lrck va aouta 3 4 5 14 0.1 f + 1f 12 +3.0 v or +5.0 v 3.3 f 3.3 f 10 k ? c c 560 ? 560 ? + + micro-controlled configuration 8 6 7 sclk 1 2 scl/cclk sda/cdin ad0/cs rst mutec 16 optional mute circuit 15 1f 0.1 f audio output a audio output b r l r l + + 10 k ? .1 f 1f 9 10 11 ref_gnd filt+ vq c= 4 fs(r 560) l r560 l + figure 16. typical connection diagram
cs4341 ds298f5 17 4. applications 4.1 sample rate range/operational mode the device operates in one of two operational modes determined by the master clock to left/right clock ratio (see section 4.2). sample rates outside the specified range for each mode are not supported. 4.2 system clocking the device requires external generation of the mast er (mclk) and left/right (lrck) clocks. the device also requires external generation of the serial clock (s clk) if the internal serial clock is not used. the lrck, defined also as the input sample rate fs, must be synchronously derived from mclk according to specified ratios. the specified ratios of mclk to lrck, along with several standard audio sample rates and the required mclk frequency, are illustrated in tables 2 and 3. *requires mclkdiv bit = 1 in the mclk control (address 00h) register. 4.2.1 internal serial clock mode the device will enter the internal serial clock mode if no low to high transitions are detected on the sclk pin for 2 consecutive periods of lrck. in this mode, the sclk is internally derived and synchronous with mclk and lrck. the sclk/lrck ratio is either 32, 48, or 64 depending upon the mclk/lrck ratio and the digital interface format selection (see table 4). operation in the internal serial clock mode is identical to operation with an external sclk syn- chronized with lrck; however, external sclk mode is recommended for system clocking appli- cations. input sample rate (fs) mode 4 khz - 50 khz single-speed mode 50 khz - 100 khz double-speed mode table 1. cs4341 speed modes sample rate (khz) mclk (mhz) 256x 384x 512x 768x* 1024x* 32 8.1920 12.2880 16.3840 24.5760 32.768 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 2. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x* 384x* 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 table 3. double-speed mode standard frequencies
cs4341 18 ds298f5 4.2.2 external serial clock mode the device will enter the external serial clock mode whenever 16 low to high transitions are de- tected on the sclk pin during any phase of the lrck period. the device will revert to internal serial clock mode if no low to high transitions are detected on the sclk pin for 2 consecutive pe- riods of lrck. 4.3 digital interface format the device will accept audio samples in several digital interface formats. the desired format is selected via the dif0, dif1 and dif2 bits in the mode control register (see section 6.2.2). for an illustration of the required relationship between lrck, sclk and sdata, see figures 17 through 19. input digital interface format selection internal mclk/lrck ratio i 2 s up to 16 or 24 bits left justified 24 bits right justified 18, 20 or 24 bits right justified 16 bits sclk/lrck ratio 512, 256, 128 (format 1) - - x 32 384, 192 xx x x48 512, 256, 128 (format 0) x x - 64 table 4. internal sclk/lrck ratio lrck sclk left channel right channel sdata +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb figure 17. cs4341 formats 0-1 - i2s up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb figure 18. cs4341 format 2 - left justified up to 24-bit data lrck sclk left channel sdata +6 +5 +4 +3 +2+1 +7 -1 -2 -3 -4 -5 lsb right channel msb lsb +6 +5 +4 +3 +2+1 +7 -1 -2 -3 -4 -5 msb lsb figure 19. cs4341 formats 3-6 - right justified
cs4341 ds298f5 19 4.4 de-emphasis the device includes on-chip digital de-emphasis. the m ode control (address 01h) bits select either the 32, 44.1 or 48 khz de-emphasis filter. figure 20 shows the de-emphasis curve for f s equal to 44.1 khz. the frequency response of the de-emphasis curve wi ll scale proportionally with changes in sample rate, fs. please see section 6.2.3 for the desired de-emphasis control. de-emphasis is only available in single-speed mode. 4.5 power-up sequence 1) hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. in this state, the control port is reset to its default settings and vq will remain low. 2) bring rst high. the device will remain in a low power state with vq low. 3) load the desired register settings while keeping the pdn bit set to 1. 4) set the pdn bit to 0. this will initiate the pow er-up sequence, which lasts approximately 50 s when the por bit is set to 0. if the por bit is set to 1, see section 4.6 for a complete description of power- up timing. 4.6 popguard ? transient control the cs4341 uses popguard ? technology to minimize the effects of output transients during power-up and power-down. this technology, when us ed with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. it is activated inside the dac when rst is enabled/disabled and requires no other external control, aside from choosing the appropriate dc-blocking capacitors. 4.6.1 power-up when the device is initially powered-up, the audio outputs, aoutl and aoutr, are clamped to agnd. following a delay of approximately 1000 sample periods, each output begins to ramp to- ward the quiescent voltage. approximately 10, 000 lrck cycles later, the outputs reach v q and audio output begins. this gradual voltage ramping allows time for the exte rnal dc-blocking capac- itors to charge to the quiescent voltage, minimizing the power-up transient. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 20. de-emphasis curve
cs4341 20 ds298f5 4.6.2 power-down to prevent transients at power-down, the device must first enter its power-down state by enabling rst or setting the pdn bit. when this occurs, audio ou tput ceases and the internal output buffers are disconnected from aoutl and aoutr. in their pl ace, a soft-start current sink is substituted which allows the dc-blocking capacitors to slowly discharge. once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 4.6.3 discharge time to prevent an audio transient at the next power-on, it is necessary to ensure that the dc-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. if not, a transient will occur when the audio outputs are initially clamped to agnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance. for example, with a 3.3 f capacitor, the mi nimum power-down time will be approximately 0.4 seconds. 4.7 mute control the mute control pin goes high during power-up initialization, reset, muting (see section 6.2.1 and 6.5.1) or if the mclk to lrck ratio is incorrect. this pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single-ended single supply system. use of the mute control function is not mandator y but recommended for designs requiring the absolute minimum in extraneous clicks and pop s. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limi ted by the external mute circuit. see the cdb4341 data sheet for a suggested mute circuit. 4.8 grounding and powe r supply arrangements as with any high resolution converter, the cs4341 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 16 shows the recommended power arrangements, with va connected to a clean supply. if the ground planes are split between digital ground and analog ground, ref_gnd & agnd should be connected to the analog ground plane. decoupling capacitors should be as close to the dac as possible, with the low value ceramic capacitor being the closest. to further minimize impedance, these capacitors should be located on the same layer as the dac. all signals, especially clocks, should be kept away fr om the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupl ing capacitors, particularly the 0.1 f, must be positioned to minimize the electrical path from filt+ and ref_gnd (as well as vq and ref_gnd), and should also be located on the same layer as the dac. the cdb4341 evaluation board demonstrates the optimum layout and power supply arrangements. 4.9 control port interface the control port is used to load all the internal regist er settings (see section 6). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i2c or spi. notes: mclk must be applied during all i2c communication.
cs4341 ds298f5 21 4.9.1 rise time for control port clock when excess capacitive loading is present on t he i2c clock line, pin 6 (scl/cclk) may not have sufficient hysteresis to meet the standard i2c rise time specification. this prevents the use of com- mon i2c configurations with a resistor pull-up. a workaround is achieved by placing a schmitt trig- ger buffer, a 74hc14 for example, on the scl line just prior to the cs4341. this will not affect the operation of the i2c bus as pin 6 is an input only. 4.9.2 memory address pointer (map) the map byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. du ring a read operation the byte transmitted after the ack will contain the data of the register pointed to by the map (see section 4.9.3 for write/read details). 4.9.2a incr (auto map increment) the device has a map auto increm ent capability enabled by the i ncr bit (the msb) of the map. if incr is set to 0, map will stay constant for su ccessive i2c writes or reads and spi writes. if incr is set to 1, map will auto increment after each byte is written, allowing block reads or writes of suc- cessive registers. default = ?0? 0 - disabled 1 - enabled 4.9.2b map0-3 (memory address pointer) default = ?0000? 4.9.3 i2c mode in the i2c mode, data is clocked into and out of the bi-directional serial control data line, sda, by the serial control port clock, scl. there is no cs pin. pin ad0 enables the user to alter the chip address (001000[ad0][r/w ]) and should be tied to va or ag nd as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000 pin 6 va scl figure 21. i2c buffer example
cs4341 22 ds298f5 4.9.3a i2c write to write to the device, follow the procedure below while adhering to the control port switching specifications in section 6. 1) initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 0. the eighth bit of the address byte is the r/w bit. 2) wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the register to be written. 3) wait for an acknowledge (ack) from the part, th en write the desired data to the register point- ed to by the map. 4) if the incr bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i2c writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus. 4.9.3b i2c read to read from the device, follow the procedure bel ow while adhering to the control port switching specifications. during this operation it is first necessary to write to the device, specifying the ap- propriate register through the map. 1) after writing to the map (see section 4.9.3a), initiate a repeated start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2) signal the end of the address byte by not issuing an acknowledge. the device will then trans- mit the contents of the register pointed to by the map. the map will contain the address of the last register written to the map. 3) if the incr bit is set to 1, the device will contin ue to transmit the contents of successive reg- isters. continue providing a clock but do not is sue an ack on the bytes clocked out of the de- vice. after all the desired registers are read, initiate a stop condition to the bus. 4) if the incr bit is set to 0 and further i2c reads from other registers are desired, it is necessary to repeat the procedure detailed from step 1. if no further reads from other registers are de- sired, initiate a stop condition to the bus. sda scl 001000 ad0 w start ack map 1-8 ack data 1-8 ack stop figure 22. i2c write
cs4341 ds298f5 23 4.9.4 spi mode in spi mode, data is clocked into the serial contro l data line, cdin, by the serial control port clock, cclk (see figure 24 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 4.9.4a spi write to write to the device, follow the procedure below while adhering to the control port switching specifications in section 1. 1) bring cs low. 2) the address byte on the cdin pin must then be 00100000. 3) write to the memory address pointer, map. this byte points to the register to be written. 4) write the desired data to the register pointed to by the map. 5) if the incr bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6) if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and repeat the procedure detailed from step 1. if no further writes to other registers are desired, bring cs high. sda scl 001000 ad0 w start ack map 1-8 ack 001000 ad0 r repeated start or aborted write ack data 1-8 (pointed to by map) data 1-8 (pointed to by map) ack stop figure 23. i2c read map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 24. control port timing, spi mode
cs4341 24 ds298f5 5. register quick reference addr function 7 6 5 4 3 2 1 0 0h mclk control reserved reserved reserved reserved reserved reserved mclkdiv reserved default 00000000 1h mode control 2 amute dif2 dif1 dif0 dem1 dem1 por pdn default 10000011 2h transition and mixing control a = b scz1 scz0 atapi4 atapi3 atapi2 atapi1 atapi0 default 00000000 3h channel a volume control mutea vola6 vola5 vola4 vola3 vola2 vola1 vola0 default 00000000 4h channel b volume control muteb volb6 volb5 volb4 volb3 volb2 volb1 volb0 default 00000000
cs4341 ds298f5 25 6. register description note: all registers are read/write in i2c mode a nd write only in spi mode, unless otherwise stated. 6.1 mclk control (address 00h) 6.1.1 mclk divide-by-2 (mclkdiv) bit 1 default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divide s the externally applied mclk signal by 2. 6.2 mode control (address 01h) 6.2.1 auto-mute (amute) bit 7 default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter out put will mute following the recept ion of 8192 co nsecutive audio samples of static 0 or -1. a sing le sample of non-zero data will rele ase the mute. detection and muting is done independently fo r each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is af fected, similar to vol- ume control changes, by the soft and zero cross bi ts in the transition and mixing control (address 02h) register. 76543210 reserved reserved reserved reserved reserved reserved mclkdiv reserved 00000000 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn 10000011
cs4341 26 ds298f5 6.2.2 digital inte rface format (dif) bit 4-6 default = 000 - format 0 (i2s, up to 24-bit data, 64 x fs internal sclk ) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 17 through 19 . 6.2.3 de-emphasis control (dem) bit 2-3 default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: implementation of the standard 15 s/50 s digital de-emphasis filter response, figure 20, requires re- configuration of the digital filter to maintain the pr oper filter response for 32, 44.1 or 48 khz sample rates. note: de-emphasis is only available in single-speed mode. 6.2.4 popguard ? transient control (por) bit 1 default = 1 0 - disabled 1 - enabled function: the popguard ? transient control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-down. please refer to section 4.6 for implementation details. 6.2.5 power down (pdn) bit 0 default = 1 0 - disabled 1 - enabled function: the device will enter a low-po wer state when this function is enab led. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation can oc cur. the contents of the control registers are retained in this mode. dif2 dif1 dif0 description format figure 0 0 0 i2s, up to 24-bit data, 64fs internal sclk 0 17 0 0 1 i2s, up to 16-bit data, 32fs internal sclk 1 17 0 1 0 left justified, up to 24-bit data, 2 18 0 1 1 right justified, 24-bit data 3 19 1 0 0 right justified, 20-bit data 4 19 1 0 1 right justified, 16-bit data 5 19 1 1 0 right justified, 18-bit data 6 19 1 1 1 identical to format 1 1 17 table 5. digital interface format
cs4341 ds298f5 27 6.3 transition and mixing control (address 02h) 6.3.1 channel a volume = channel b volume (a = b) bit 7 default = 0 0 - disabled 1 - enabled function: the aouta and aoutb volume levels are independently controlled by the a and the b channel vol- ume control bytes when this function is disabled . the volume on both aouta and aoutb are de- termined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 6.3.2 soft ramp and zero cross control (szcx) bit 5-6 default = 10 00 - immediate changes 01 - changes on zero crossings 10 - soft ramped changes 11 - soft ramped changes on zero crossings function: immediate changes when immediate changes is selected all level changes will ta ke effect immediately in one step. changes on zero crossings changes on zero crossings dictates that signal level changes, either by attenuation changes or mut- ing, will occur on a signal zero crossing to minimi ze audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a ze ro crossing. the zero cross function is independent- ly monitored and implemented for each channel. soft ramped changes soft ramped changes allows level changes, both muting and attenuation, to be implemented by in- crementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1db per 8 left/right clock periods. soft ramped changes on zero crossings soft ramped changes on zero crossings dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps implemented on a signal zero crossing. the 1/8 db level change will occur after a ti meout period between 512 and 1024 samp le periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enco unter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 76543210 a = b szc1 szc0 atapi4 atapi3 atapi2 atapi1 atapi0 01001001
cs4341 28 ds298f5 6.3.3 atapi channel mixi ng and muting (atapi) bit 0-4 default = 01001 - aouta = left channel, aoutb = right channel (stereo) function: the cs4341 implements the channel mixing functions of the atapi cd-rom s pecification. refer to table 6 and figure 25 for additional information. atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 0 1 1 0 0 a[(l+r)/2] mute 0 1 1 0 1 a[(l+r)/2] br 0 1 1 1 0 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute bl/2 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(ar+bl)/2] 11000 al mute 11001 al br 11010 al bl 1 1 0 1 1 al [(al+br)/2] 11100 al/2 mute 1 1 1 0 1 [(al+br)/2] br 1 1 1 1 0 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 6. atapi decode
cs4341 ds298f5 29 6.4 channel a volume co ntrol (address 03h) same as channel b volume control. 6.5 channel b volume co ntrol (address 04h) 6.5.1 mute (mute) bit 7 default = 0 0 - disabled 1 - enabled function: the digital-to-analog conv erter output will mute wh en enabled. the quiescen t voltage on the output will be retained. the muting function is affected, similar to attenuation changes, by the soft and zero cross bits in the transition and mixing contro l (address 02h) regi ster. the mutec will go active dur- ing the mute period if the mute f unction is enabled for both channels. 76543210 mutex volx6 volx5 volx4 volx3 volx2 volx1 volx0 00000000 ? a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 25. atapi block diagram
cs4341 30 ds298f5 6.5.2 volume (volx) bit 0-6 default = 0 db (no attenuation) function: the digital volume control allows the user to attenuat e the signal in 1 db increments from 0 to -90 db. volume settings are decoded as shown in table 7. the volume changes are implemented as dictated by the soft and zero cross bits in the transition and mixing control (address 02h) register. all volume settings less than - 94 db are equivalent to enabling the mute bit. binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 7. example digital volume settings
cs4341 ds298f5 31 7. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), includin g distortion components. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to th e rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to- noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distor tion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the elec tronic industries associati on of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter?s output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c.
cs4341 32 ds298f5 8. package dimensions 8.1 soic inches millimeters dim min nom max min nom max a 0.053 0.064 0.069 1.35 1.63 1.75 a1 0.004 0.006 0.010 0.10 0.15 0.25 b 0.013 0.016 0.020 0.33 0.41 0.51 c 0.0075 0.008 0.010 0.19 0.20 0.25 d 0.386 0.390 0.394 9.80 9.91 10.00 e 0.150 0.154 0.157 3.80 3.90 4.00 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.228 0.236 0.244 5.80 6.0 6.20 l 0.016 0.025 0.050 0.40 0.64 1.27 0 4 8 0 4 8 jedec #: ms-012 controling dimensi on is millimeters e 16l soic (150 mil bo dy) package drawing d h e b a1 a c l seating plane 1
cs4341 ds298f5 33 8.2 tssop notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. 9. package thermal resistance inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.193 0.1969 0.201 4.90 5.00 5.10 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters package symbol min typ max units soic (for multi-layer boards) tssop (for multi-layer boards) ja ja - - 74 89 - - c/watt c/watt 16l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs4341 34 ds298f5 10.references cdb4341 evaluation board datasheet 11.revision history revision changes f4 added lead-free packaging information f5 corrected dimension e in tssop package drawing va lue for nom millimeters from 0.065 to 0.65 contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest to you, go to www.cirrus.com/corporate/contacts/sales.cfm important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, mili tary applications, produc ts surgically implanted into the body, automotive safety or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

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